This will be a short post. The tagline mentions jumper because this write-up is about reverse engineering the L2 cache jumpers on a 1990's Pentium (P54) motherboard. There are more jumpers that need some figuring out, and they will not appear until a future write-up.
While sorting through 'tech' I had stowed for future hobbies, I found myself unable to parrt with an AT (clone) case from what was once a 386DX/25 on which I first learned MS-DOS, Windows 3.1 and Microsoft Publisher.
That AT case no longer has anything from its "386" days except for the original two floppy drives and a power supply. At some point I had stashed a rescued Pentium motherboard in the case - Full Yes Incorporated SIS P5 PCI; the motherboard had 256K of 15ns cache installed (eight chips) and a single cache chip with 25ns rating. The motherboard functioned only with cache disabled.
With the cache disabled in BIOS, I uncovered another problem. Since stashing the motherboard a decade ago, the Dallas CMOS RTC battery had faded. I was now greeted with a NMI error. A site hinted that bad CMOS can potentially interfere with being able to establish a healthy cache, resulting in memory errors and a dreaded NMI on boot. NMI errors are also reported as happening with bad disk blocks or a corrupted boot sector.
I ordered a new RTC from DigiKey, installed it, and my problems were not solved.
Replacing the RTC allowed the CMOS to keep settings which meant the next challenge was to find out why I was getting the dreaded NMI. The NMI ended up being a simple fix - either install parity SIMMs or disable the parity check in the BIOS. I tried both ways, but I had yet another problem. Upon getting to POST, the system hanged when the cache was enabled.
The motherboard uses a SIS 50x chipset. I read up on SIS chipsets and learned that most of the SIS motherboards supported 1MB to 2MB of cache. This motherboard has 20 sockets for DIP32 cache chips.
I placed an order for 128Kx8's and upon receiving them, tested them in my Xgecu TL866ii to eliminate bad modules.
I installed the cache chips and the system would hang on POST with either a report of 0K or 64K of cache. I fussed with the jumpers in proximity to the cache sockets and found settings which claimed 2MB of alleged cache on POST; however, the system still hanged after POST or shortly after reaching a prompt in FreeDOS.
I read about how someone had managed to revise their system board - from the same era and same chipset - to accommodate 2MB of cache despite being manufactured with support for 1MB. That gave me incentive to pull out a multimeter and begin ohming connections on the system board. I discovered that a block of jumpers positioned between the TAG RAM sockets and the CPU socket were not anything other than jumpers for specifying the TAG RAM configuration. Up until this point I suspected they were settings for CPU or cache voltage. Instead, neither. Before filling all sockets, I double-checked that the TAG RAM sockets would accept 128Kx8's. Other SIS system board manuals hinted that 1MB of cache with 128Kx8's requires a single 64Kx8 TAG SRAM. Two banks of 1MB would follow to equal two 64Kx8's.
Well, shoot; I only ordered 128Kx8's.
A 128Kx8 will address up to line A16, but what if the pin for A16 is neither connected to ground nor Vcc - in fact, not connected at all? If that happened to be the case, I would need to short them ground; otherwise it might float between either of two 64K banks on the the 128Kx8 DIP32. If they had been floating, that might explain the variance between 0K and 64K, or now with the jumpers configured to 2MB, wavering between 0K and 2MB.
A check with the multimeter showed line A16 of both TAG SRAM sockets was properly hooked to ground. But the findings for the middle set of jumpers - JP7, JP8, JP9 and JP10 showed some measurements I did not immediately follow. JP7, JP8 and JP10 all had been in a position to short to ground. JP9 jumpered A13 to Vcc (+5V). The explanation for this became clear when I looked up the pin out for a DIP28 8Kx8. The pin that feeds A13 on a 128Kx8 is actually the Vcc for an 8Kx8. From this I concluded that if I shifted JP7, JP8 and JP10 away from grounding, and JP9 away from Vcc, the configuration of twenty 128Kx8's would give me 2MB of fully functional cache. Indeed it does.
I hope this helps someone else.
Here are the settings I established to configure a full 2MB cache using ISSI 61C1024-15Ns DIP32's
JP7 [32]1 means if 3-2-1 then [32] are jumpered and 1 is NC.
JP8 [32]1 there are no markings for pin numbers so the order
JP9 [32]1 is purely based on JP4's position with respect to
JP10 [32]1 the other jumpers on the system board.
[32]1 JP1
[32]1 JP2
[32]1 JP3
[54][32]1 JP4
That's all. Thanks for reading!
